Current sub-nanometer scaling faces three primary physical barriers: electron-hole mobility imbalance, Front-End-of-Line (FEOL) masking complexity, and high interconnect RC delay. This architecture resolves these constraints by separating n-channel and p-channel fabrication onto two dedicated wafers and vertically stacking them over a silicon host. By integrating Gallium Arsenide (GaAs) and Germanium (Ge), the design naturally incorporates optical waveguides to bypass electrical interconnect limits.
1. Single-Type Wafer Processing
Traditional planar and FinFET CMOS manufacturing requires 60 to 90+ masking steps. Over half of these steps are block-out masks used to isolate n-wells from p-wells and prevent cross-contamination during doping and work-function metal deposition.
This architecture decouples the process into two independent 300 mm Silicon host wafers:
Wafer 1 (n-FET Tier): Thin-film GaAs is grown on the silicon base via Selective Area Epitaxy (SAE). This wafer is dedicated entirely to high-electron-mobility n-channel logic.
Wafer 2 (p-FET Tier): Thin-film Ge is grown on a separate silicon base, dedicated entirely to high-hole-mobility p-channel logic.
Because each wafer processes only a single transistor polarity, block-out masks are eliminated. Every active zone on Wafer 1 receives identical n-type processing, and Wafer 2 receives identical p-type processing. This reduces the mask count to approximately 25-35 steps per tier, lowering the statistical defect density. Furthermore, because thin-film GaAs and Ge are grown epitaxially on standard silicon, the design bypasses the prohibitive costs and mechanical limitations of bulk compound wafers.
2. Low-Temperature 3D Vertical Fusion
Once both wafers complete FEOL processing independently, they are integrated vertically to form a 3D Complementary FET (3D-CFET) structure.
Wafer 2 is passivated with an atomic layer of silicon dioxide, inverted, and aligned over Wafer 1. The wafers undergo direct oxide-to-oxide fusion bonding at low temperatures (<300°C). This low thermal budget ensures that the dopant profiles and crystal structures of the pre-fabricated GaAs and Ge channels remain intact.
After bonding, the bulk silicon handling substrate of Wafer 2 is cleaved or etched away, leaving only the micro-thin active Ge tier anchored above the GaAs tier. Standard vertical vias are etched through the thin bonding oxide to connect the drains of the top and bottom tiers. By stacking the p-FET directly over the n-FET, the lateral isolation gap required in standard 2D CMOS is eliminated, reducing the physical logic cell footprint by approximately 50%.
3. Embedded Photonic Architecture
The integration of GaAs and Ge solves the electronic mobility imbalance, but it also natively provides the materials required for on-chip optoelectronics. GaAs acts as a direct-bandgap light emitter, while tensile-strained Ge acts as a highly efficient Short-Wave Infrared (SWIR) photodetector.
The inter-tier dielectric (SiO₂) bonding layer serves a dual purpose as a high-index-contrast optical waveguide. This enables a hybrid optical clocking system:
1. Generation: Embedded GaAs micro-lasers generate a master optical clock pulse.
2. Distribution: The signal routes through the transparent SiO₂ waveguides. Because photons travel through the dielectric without charging wire capacitance, the interconnect RC delay is zero.
3. Conversion: Local Ge photodiodes receive the optical pulse and drive short, localized copper clock trees.
In large processors, the global electrical clock distribution network consumes 30% to 50% of the total dynamic power (P = C V² f). Replacing the global copper tree with optical distribution reclaims this power budget and eliminates clock skew across the die.
4. Yield and Economic Synthesis
While this architecture requires dual-epitaxy processing, the system-level gains offset the front-end manufacturing overhead:
Die Density: Halving the logic cell footprint yields twice as many functional dies per 300 mm silicon wafer.
Material Efficiency: Consuming precursor gases to grow sub-micron active channels on silicon avoids the extreme substrate costs of bulk native GaAs and Ge.
Cycle Time: Stripping tens of block masks from the lithography cycle reduces queue times and physical defect accumulation.
The resulting platform maximizes carrier mobility and drive-current symmetry while natively supporting optical data buses, resolving the primary physical scaling limits of conventional single-material CMOS.
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